Technical Speak- From the Weak Write Test Mode Saga

“You have excellent PowerPoint skills.” Joe Schutz had requested two slides on Weak Write Test Mode to include in a presentation to his manager. On loan to Joe’s microprocessor design team I reported into him via Doug Guddat who managed the memory design group. Joe had asked me directly for the slides and I delivered….

Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map

While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance….

Don’t Fail Good Cells: Part of the Weak Write Test Mode Saga

Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the…

Studying High-Speed I/O Failures: Tales from the Intel I/O Test Road Map

After successful deployment of AC I/O loopback for single-ended interfaces, we rapidly had to prepare for High Speed I/O (HSIO) circuitry. The HSIO derived from Serializer/Deserializer (aka SerDes) interfaces commonly used in telecommunications. Computer systems’ thirst for higher data rates drove the adoption of this interface architecture. These I/O circuits had significant differences from single-ended…