Innovation I/O Timings, a Precursor—Tales from the Intel I/O Test Road Map

One of these things is not like the others

Growing up I heard the story of the Archimedes and his moment of inspiration in the bath. “Eureka” he declared racing to inform the King of his solution. This story propels the myth that great ideas come out of thin air. There is usually a lot more work and time behind an innovative idea. In addition, some notion takes hold of the person determined to see it to fruition. Reinventing testing for IO timings started with an annoyance and sliding timings.

Mike Tripp knew the I/O timing test had to change. The work began in 1994-1995 as he led the KIT team for the Pentium Pro (aka P6) product family. He grappled with the dilemma that pitted design margin versus test method. The tight timings test method required a design performance significantly better than the specification. A shift in system timings in future PCs added pressure to solving this impasse.

P6 systems used common clock timings for the communication between the microprocessor and the memory controller chip (MCH). The synergy between increasing internal clock speed and external data rates pointed to the short comings of common clock (CC) timings. Sending signals across the inexpensive FR4 based system boards compounded the deficits of CC timings. To continue FR4 board usage and support higher data rates source synchronous (SS) timings came to personal computer design. In Mike’s engineering mind this change sealed the fate of tight timings test method.

In the late 1990’s all Automatic Test Equipment (ATE) spoke common clock timings. Willamette, code name for the first Pentium 4 microprocessor and Camino, its companion MCH chipset would be the first to use source synchronous timings. With CC timing’s all timing specifications related to a common clock. With SS timings a strobe signal associated with a set of data signals would be sent, one can look at it as supplying a local clock. The specifications were relative to a set of signals not a common clock. How could an ATE with just a common clock perspective be made to measure the specs for this new interface? With engineers the saying “Where’s there a will there’s a way” can lead to a solution.

Mike had a white board session with his manager John Coulter– Could we move the tester strobe signals until we saw the difference? While not intimately familiar with ATE operation Mike always asked good questions. John managed the team of test engineers responsible for microprocessors, he knew enough that this would be possible. Mike pushed on and worked out a methodology which could use the current ATE to accurately measure the timings. He dubbed it “Sliding Window” as the method relied upon sliding two sets of strobe timings. As often happens when solving a problem with what’s on hand the resulting solution while effective was not efficient or economical.

While silicon design validation could tolerate the increased test time, the sliding window methodology would not be consumable during manufacturing test. Mike persisted on solving the manufacturing test challenge, the annoyance it had once been only became more pronounced. John pointed him to the relatively new department, Sort Test Technology Development (STTD) as a better home for solving this problem.

As a technology drive organization STTD focused on roadmaps not product timelines. It maintained a horizontal view well suited to an innovation in I/O timings. The Pentium 4 (aka Willamette) would not be the only computer chip requiring a new I/O Test method. Mike though leveraged his relationships with the Oregon based microprocessor team to begin the reinvention. He knew both the I/O design team lead, Tim Frodsham, and he had just worked for John Coulter who managed the large product development engineering team. These relationships made previously described empirical experiment and defective circuit simulations possible. These studies provided fodder for innovative thinking:

  • Failed Timings impacted primarily a single I/O
  • Failed output timings were significantly higher than failed input timings.

The knowledge that one I/O failed matches well with the standard single stuck at fault model. However, primarily does not equal100%.  The new test method needed to find defects that impacted multiple I/Os. A solution path began to formulate which focused on finding defective timings. This shift from verifying timings to detecting defective timings opened up considering implicit methods. Fundamental the new method needed stress the timings.

At first blush one would think, well just increase the data rate of the interface until it fails. Not unlike separating out microprocessors by speed. Yet, for input timings the method had to measure within the 100 picoseconds (10E-10 seconds) range; this translated to running the interface at 10 GHZ. First, no reliable clocking existed on the tester to support that clock rate. Also the circuitry in the interface simply wouldn’t go that fast. Pushing the frequency of the IO– not plausible.

Stressing the timings sounded like “shifting the timings.” We only needed to find the bad timings. This thinking resulted in a method which focused on “one of these things is not like another.” Source synchronous timings naturally led Mike to consider such an approach. In SS timings a group of data pins was linked to a strobe pin(s). When a data timing became longer/shorter it would stick out.  If the strobe signal became longer/shorter all the data timings would be offset.  So knowing the distribution of the “new timing test” would make that one stick out as well. This new method required

  • Groups of pins with the same expectation
  • Distribution of Timings
  • Comparing timings to each other

Changing and comparing timings had a familiar ring to it. Sounded like “shifting the timings,” and that had been fundamental to the sliding window technique that Mike and John had developed for design validation. This method explicitly measured the timings and had already been deemed too expensive for manufacturing test. What if the strobe timings could be changed internally?  Hmm one innovation leads to another by adapting the concept to be on the die.

A patent was filed on the idea of changing the timings on the die.  Next up- could we get some experimental silicon to verify the concepts prior to moving to an actual product?

Have a productive day,

Anne Meixner

Dear Reader, What memory or question does this piece spark in you? What’s your point of view of on developing a solution? Please share your comments or stories below. You too can write for the Engineers’ Daughter- See Contribute for more Information.

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