Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map

From “Computer-aided Design for VLSI Circuit Manufacturability”; W. Mally, Proceedings of the IEEE, 1990 vol 78, Issue 2

While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance. With this design practice in mind we believed that structural defects caused the majority of the failures. I focused on layout deformations that resulted in unintended connections in the I/O circuit—i.e. shorts.

Inductive Fault Analysis (IFA) predicts bad circuit behavior by simulating a probable defective circuit. Via Intel’s membership in Semiconductor Research Corporation (SRC,) I had access to a computer aided design (CAD) tool that analyzed circuit layout to produce a ranked list of faults. Developed by Professor Joel Ferguson’s research team at University of California Santa Cruz, CARAFE evaluated impact of spot defects by expanding layout to assess critical area. Critical area represents an area in which a process deformation of radius R can fall and cause a change in the physical layout. In turn, this represents a defective circuit. By applying the probability distribution of defects per semiconductor layer to the critical area, the relative probability of a defect’s occurrence can be known. This enables engineers to focus on the most likely behaviors.

The classic defect radius distribution curve has a peak at a known radius. In a semiconductor fabrication facility, engineers expend an immense amount of effort to monitor and reduce defects. While manufactured in “clean rooms” to reduce the introduction of particles, the processing steps of depositing and etching materials generate particle themselves. Like other fab companies, Intel tracked defect size and distribution so we had fairly accurate statistics to enter into CARAFE. The output: a ranked list of faults.

The ranked list of faults would next be simulated. I delved into Intel’s in-house circuit simulation tool to understand how I could automate simulation. Very similar to what I had to do for my PhD thesis work, I wrote scripts that would use the fault list to insert the shorts within the good circuit netlist. I modeled the short as a resistor of value R. I could then vary R to reflect a range of physical deformations (1 ohm to 10,000 ohms.) The circuit simulations matched the timing specs examined on the tester. I looked at the output timings’ TCO and the input timings’ set-up and hold (see figure below.)

When I shared my results of defective circuits and their behavior, nothing about the circuit behavior surprised to the I/O circuit designers. “Makes sense,” “right”–they knew the circuit operation and the purpose of every connection. The ranked fault list caught them off guard. The largest contributors to timing failures happened to be circuitry that had been added solely for debug purposes. I vaguely recall these were the top 10 defects. Their reaction: “My God, this circuitry isn’t needed any more. Maybe we should take this out in a future design.” One has to be careful of what gets copied.

When Mike and Spass wrapped up their empirical study of failures, Mike sent a true fail to a failure analysis lab. As it had low priority it took many months for report. Eventually he came to my office to show me that the defect found was in that “extra” circuitry. I smiled–it came as no surprise to me. I had faith in the Inductive Fault analysis approach; one could say that the defect-based approach formed the basis of my engineering religion.

Have a productive day,

Anne Meixner

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