In one’s engineering career the opportunity to work on a Sexy Hard Problem may occur only once. Your chances increase when you happen to be present for an engineering revolution. Just ask the engineers, scientists and computers who supported NASA’s mission to the Moon. Because I worked in the test manufacturing technology department, I found myself in the middle of a minor revolution. In the late 1990s Moore’s Law began to tax the test cost–more transistors to test with the goal of keeping the test costs flat. Faster frequencies, both internal and on the interface testing, could mean development of faster Automatic Test Equipment (ATE.) The revolution was to test with cheaper equipment.
Mike Tripp moved from a design organization to Sort Test Technology Development. His motivation: Input/output (I/O) testing methods had an adverse impact on circuit designers. The solution, AC IO Loopback, supported the goal of flat test costs by enabling older and slower ATE, which had less timing precision to test than the I/O circuits specifications required. Just like Weak Write Test mode, (provide link) AC IO Loopback’s signs that the problem was sexy hard:
- The solution has multiple engineering benefits: reduce test time, provide designers more margin, enable slower ATE to test faster IO, two measurements replace four measurements.
- The solution can be applied to every single product with that type of circuitry at your company.
- The solution can be extended to different IO architectures.
- Numerous patent applications are filed.
- Lots of questions are asked at the presentation.
- One of the many internal conference papers is awarded best paper.
- The external conference paper is awarded best paper.
- You’re asked to check the dates on the invention disclosure to compare to IBM’s data on a similar idea.
This minor revolution resulted in over a decade of development to support Intel’s IO Test Road Map. As a long time traveler on this road map, I have many tales to share.
Have a productive day,
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The Intel paper on adding a structural tester published in 2002 can be found on the IEEE data base. Here is the abstract:
This paper traces the evolution of the distributed test strategy at Intel, covering both the tester platform, which is now on the 2nd generation, as well as the parallel evolution of the test content, which is optimized for this platform. We describe the distribution of Pentium/spl reg/ 4 processor test content between structural and functional platforms, associated fallout, and key issues encountered with content migration. Finally, we discuss future test content and platform trends as shaped by increasing device complexity and defect types.
You can read the Intel AC IO Loopback patent here.
IBM’s work on IO testing was described by Pam Gillis and her colleagues in a conference paper entitled: Delay test of chip I/Os using LSSD boundary scan