After successful deployment of AC I/O loopback for single-ended interfaces, we rapidly had to prepare for High Speed I/O (HSIO) circuitry. The HSIO derived from Serializer/Deserializer (aka SerDes) interfaces commonly used in telecommunications. Computer systems’ thirst for higher data rates drove the adoption of this interface architecture. These I/O circuits had significant differences from single-ended interfaces, which AC I/O loopback supported. The feature list included:
- Unidirectional signaling
- Point-to-point interconnect on the system board
- Differential signaling
- 8/10-bit encoding
- Protocol aware interfaces to move from sleep mode to active transmission
- Training as part of the wake-up procedure to compensate circuitry to strobe and impedance
- Significantly higher data rates than any of Intel’s testers
In summary, these circuits were a heck of a lot more complicated.
We started the pathfinding work in 2001 to prepare for an introduction of products in 2005. I led a small team of engineers for this work. In graduate school I learned that the best way to approach testing is to understand how things fail. Hence, we began a study of defect’s impact on circuit performance. A test chip design team gave us access to their 3GIO circuits (aka Third Generation I/O.) Inserting defects into a good circuit and simulating the resulting performance required multiple fault simulations. We used a heuristic to insert defects into the circuit, based upon the schematic connections. We had developed a set of scripts to perform this function.
To simplify the analysis, we split the 3GIO prototype circuit into sub-circuits for each team member. I took on the data clock recovery circuitry, Pat took on the driver circuit, and Bob took on the receiver circuitry. The Data Clock recovery circuit had an implementation based upon a clock mixer, which was different than another over-sampling technique. Stay tuned for what I found.
Have a productive day,
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