Pathfinding at a technology company can be considered a form of research—research on an explicit engineering problem. Often it can be a long way off before the problem really needs to be solved. Sometimes it’s quite by accident that a solution developed for one problem solves a similar problem further down the roadmap. In this…
Category: Their Stories
Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map
While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance….
The True Nature of I/O Timing Failures: Tales from the Intel I/O Test Road Map
Measurements have errors due to accuracy and precision of the equipment. In semiconductor testing, when setting a pass/fail limit one can set it such that it fails a few good parts–dubbed overkill, or it passes a few bad parts–dubbed underkill (aka escapes.) One errs on the side of protecting one’s customer, i.e. fail good parts…
Apprenticed to Study Manufacturing Defects–A Graduate School Story
In the Fall of 1988 I started my PhD studies in Electrical and Computer Engineering at Carnegie Mellon University. Soon, I began to have an inkling of why Professor Wojciech Maly had invited me to be his student. Attending the weekly research group meeting exposed me to the thesis topics of the other students….
Don’t Fail Good Cells: Part of the Weak Write Test Mode Saga
Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the…
A Reminder that Subroutines Save Time: Tales From the Intel I/O Test Road Map
Programming has never been my favorite task as an engineer. It may relate to the fact that each new project came with learning yet another language. The activation energy to start up always appeared more daunting then it would turn out to be. Ironically, my programming skills helped in getting my summer job at NBS…
36 Views of Conversations with my PhD Advisor: View 1–Grad School Story
My graduate school applications resulted in several PhD programs to choose from. Naturally, I visited each school. After an eight-hour drive from Poughkeepsie, NY to Pittsburgh, PA, I found myself across a desk from Wojciech Maly. The acceptance letter indicated he would be my advisor. He took time from teaching his VLSI design project class to…
Studying High-Speed I/O Failures: Tales from the Intel I/O Test Road Map
After successful deployment of AC I/O loopback for single-ended interfaces, we rapidly had to prepare for High Speed I/O (HSIO) circuitry. The HSIO derived from Serializer/Deserializer (aka SerDes) interfaces commonly used in telecommunications. Computer systems’ thirst for higher data rates drove the adoption of this interface architecture. These I/O circuits had significant differences from single-ended…
A Second Sexy Hard Problem: Tales from the Intel I/O Test Road Map
In one’s engineering career the opportunity to work on a Sexy Hard Problem may occur only once. Your chances increase when you happen to be present for an engineering revolution. Just ask the engineers, scientists and computers who supported NASA’s mission to the Moon. Because I worked in the test manufacturing technology department, I found…
Finding Purpose: A Graduate School Story
Pursuing a PhD in engineering requires perseverance, and having a purpose helps when you have a rough day. I delayed graduate school because the statement of purpose portion of the application made me realize that I wasn’t sure of my purpose. So I took the risk to wait on a PhD as I began an…