As Rick Buskens and I ventured back from eating ice cream on N Craig St street I shared my thesis topic and the simulation challenge it presented. To explore the topic of analog fault modeling I needed to simulate 1000’s of circuits. For every operational op-amp I would be inserting shorts modeled as a 1-ohm…
Tag: Economy vs Efficiency vs Efficacy
The Long Path to 20 Bytes of Firmware
When I began my approach for a By-Pass Lock screen solution, I knew that the USB/PCI Express Bridge chip I was using had the capability to enable DMA attacks. But I wasn’t sure how to configure it properly. In the end 20 Bytes of firmware did it. But getting to the 20 bytes of firmware…
Make it Light
So a while ago I put together a hardware security project. The device I was building was a PCIExpress device to do DMA (Direct Memory Access) attacks on a computer. The idea being you would have a card that you could put in a slot into the computer. Then this card would basically use its…
Innovation on I/O Timings, a Precursor—Tales from the Intel I/O Test Road Map
Growing up I heard the story of the Archimedes and his moment of inspiration in the bath. “Eureka” he declared racing to inform the King of his solution. This story propels the myth that great ideas come out of thin air. There is usually a lot more work and time behind an innovative idea. In…
Innovation I/O Timings, a Precursor—Tales from the Intel I/O Test Road Map
Growing up I heard the story of the Archimedes and his moment of inspiration in the bath. “Eureka” he declared racing to inform the King of his solution. This story propels the myth that great ideas come out of thin air. There is usually a lot more work and time behind an innovative idea. In…
Pathfinding Work on No-Touch Leakage Testing, Part 3: Tales from the Intel I/O Test Road Map
On Willamette we proved that AC I/O loopback testing worked. The AC I/O loopback provided the designers margin. I had completed the groundwork for testing I/O leakage on the structural tester using the RC decay leakage method (link to previous post.) Alas, we didn’t get a chance to try it out on the structural tester….
Pathfinding Work on No-Touch Leakage Testing, Part 2: Tales from the Intel I/O Test Road Map
With AC I/O Loopback test method Intel, had embarked upon not relying upon Automatic Test Equipment (ATE) to explicitly test for Input/Output (I/O) circuit characteristics. The device under test (DUT) remained connected to ATE and tests like I/O voltage levels and I/O pin leakage were still tested by the ATE. As noted in an earlier post,…
Pathfinding Work On No-Touch Leakage Testing, Part 1 of 3: Tales from the Intel I/O Test Road Map
Pathfinding at a technology company can be considered a form of research—research on an explicit engineering problem. Often it can be a long way off before the problem really needs to be solved. Sometimes it’s quite by accident that a solution developed for one problem solves a similar problem further down the roadmap. In this…
Don’t Fail Good Cells: Part of the Weak Write Test Mode Saga
Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the…
A Reminder that Subroutines Save Time: Tales From the Intel I/O Test Road Map
Programming has never been my favorite task as an engineer. It may relate to the fact that each new project came with learning yet another language. The activation energy to start up always appeared more daunting then it would turn out to be. Ironically, my programming skills helped in getting my summer job at NBS…