With AC I/O Loopback test method Intel, had embarked upon not relying upon Automatic Test Equipment (ATE) to explicitly test for Input/Output (I/O) circuit characteristics. The device under test (DUT) remained connected to ATE and tests like I/O voltage levels and I/O pin leakage were still tested by the ATE. As noted in an earlier post,…
Tag: Intel
Pathfinding Work On No-Touch Leakage Testing, Part 1 of 3: Tales from the Intel I/O Test Road Map
Pathfinding at a technology company can be considered a form of research—research on an explicit engineering problem. Often it can be a long way off before the problem really needs to be solved. Sometimes it’s quite by accident that a solution developed for one problem solves a similar problem further down the roadmap. In this…
Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map
While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance….
The True Nature of I/O Timing Failures: Tales from the Intel I/O Test Road Map
Measurements have errors due to accuracy and precision of the equipment. In semiconductor testing, when setting a pass/fail limit one can set it such that it fails a few good parts–dubbed overkill, or it passes a few bad parts–dubbed underkill (aka escapes.) One errs on the side of protecting one’s customer, i.e. fail good parts…
Don’t Fail Good Cells: Part of the Weak Write Test Mode Saga
Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the…
A Reminder that Subroutines Save Time: Tales From the Intel I/O Test Road Map
Programming has never been my favorite task as an engineer. It may relate to the fact that each new project came with learning yet another language. The activation energy to start up always appeared more daunting then it would turn out to be. Ironically, my programming skills helped in getting my summer job at NBS…
Studying High-Speed I/O Failures: Tales from the Intel I/O Test Road Map
After successful deployment of AC I/O loopback for single-ended interfaces, we rapidly had to prepare for High Speed I/O (HSIO) circuitry. The HSIO derived from Serializer/Deserializer (aka SerDes) interfaces commonly used in telecommunications. Computer systems’ thirst for higher data rates drove the adoption of this interface architecture. These I/O circuits had significant differences from single-ended…
A Second Sexy Hard Problem: Tales from the Intel I/O Test Road Map
In one’s engineering career the opportunity to work on a Sexy Hard Problem may occur only once. Your chances increase when you happen to be present for an engineering revolution. Just ask the engineers, scientists and computers who supported NASA’s mission to the Moon. Because I worked in the test manufacturing technology department, I found…
Attributions in the Engineering Community—From the Weak Write Test Mode Saga
I had approximately 500 Pentium (P54CS) parts that uniquely failed the Weak Write Test Mode (WWTM.) In the lab I ran the test on an IMS debug tester to diagnose the failing cell location–engineers always want more data. I talked to engineering managers regarding additional tests. The resulting list would require help from other engineering…
My First Patent–From the Weak Write Test Mode Saga
Not all great ideas turn into patents; they simply are not novel enough to warrant the effort. Some ideas are so great that a company decides to keep them as a trade secret. The following exchange I had with Greg Taylor instructed me on how to determine if an invention should be patented: “Would other…