So a while ago I put together a hardware security project. The device I was building was a PCIExpress device to do DMA (Direct Memory Access) attacks on a computer. The idea being you would have a card that you could put in a slot into the computer. Then this card would basically use its…
Tag: Solving the Sexy Hard Problem
Innovation on I/O Timings, a Precursor—Tales from the Intel I/O Test Road Map
Growing up I heard the story of the Archimedes and his moment of inspiration in the bath. “Eureka” he declared racing to inform the King of his solution. This story propels the myth that great ideas come out of thin air. There is usually a lot more work and time behind an innovative idea. In…
Innovation on IO Timings with the Test chips—Tales from the Intel I/O Test Road Map
Our investigative work into the true nature of IO timing failures informed us of the current state of the art testing and the likely source of defects. The challenge to test the timings without using the traditional ATE approach was on. We even had an approach- stressing the timings on the die and self-compare. To…
Pathfinding Work on No-Touch Leakage Testing, Part 3: Tales from the Intel I/O Test Road Map
On Willamette we proved that AC I/O loopback testing worked. The AC I/O loopback provided the designers margin. I had completed the groundwork for testing I/O leakage on the structural tester using the RC decay leakage method (link to previous post.) Alas, we didn’t get a chance to try it out on the structural tester….
Pathfinding Work on No-Touch Leakage Testing, Part 2: Tales from the Intel I/O Test Road Map
With AC I/O Loopback test method Intel, had embarked upon not relying upon Automatic Test Equipment (ATE) to explicitly test for Input/Output (I/O) circuit characteristics. The device under test (DUT) remained connected to ATE and tests like I/O voltage levels and I/O pin leakage were still tested by the ATE. As noted in an earlier post,…
Pathfinding Work On No-Touch Leakage Testing, Part 1 of 3: Tales from the Intel I/O Test Road Map
Pathfinding at a technology company can be considered a form of research—research on an explicit engineering problem. Often it can be a long way off before the problem really needs to be solved. Sometimes it’s quite by accident that a solution developed for one problem solves a similar problem further down the roadmap. In this…
Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map
While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance….
The True Nature of I/O Timing Failures: Tales from the Intel I/O Test Road Map
Measurements have errors due to accuracy and precision of the equipment. In semiconductor testing, when setting a pass/fail limit one can set it such that it fails a few good parts–dubbed overkill, or it passes a few bad parts–dubbed underkill (aka escapes.) One errs on the side of protecting one’s customer, i.e. fail good parts…
Don’t Fail Good Cells: Part of the Weak Write Test Mode Saga
Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the…
A Second Sexy Hard Problem: Tales from the Intel I/O Test Road Map
In one’s engineering career the opportunity to work on a Sexy Hard Problem may occur only once. Your chances increase when you happen to be present for an engineering revolution. Just ask the engineers, scientists and computers who supported NASA’s mission to the Moon. Because I worked in the test manufacturing technology department, I found…