Make it Light

So a while ago I put together a hardware security project. The device I was building was a PCIExpress device to do DMA (Direct Memory Access) attacks on a computer. The idea being you would have a card that you could put in a slot into the computer. Then this card would basically use its…

Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map

While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance….

Don’t Fail Good Cells: Part of the Weak Write Test Mode Saga

Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the…

A Second Sexy Hard Problem: Tales from the Intel I/O Test Road Map

In one’s engineering career the opportunity to work on a Sexy Hard Problem may occur only once. Your chances increase when you happen to be present for an engineering revolution. Just ask the engineers, scientists and computers who supported NASA’s mission to the Moon. Because I worked in the test manufacturing technology department, I found…