Alternatives to a 500 Millisecond Pause: Part I of the Weak Write Test Mode Saga

Several colorful arrow signs pointing in different directions representing different priorities in managing production processes - quality, speed, efficiency, and cost

Efficiencies in engineering solutions are not a matter of just doing it faster; they often come about by looking at the problem from a different perspective. Such is the genesis of the move from a one-second test to a 100-millisecond test solution. Testing electronics has evolved over the decades from testing for goodness to detecting badness because it’s more efficient. I became fascinated with semiconductor defects when I worked at IBM–so fascinated that I purposely studied them for my doctorate at Carnegie Mellon University. At Intel I had opportunities to put this fascination and the CMU training to use, garnering impactful results. Weak Write Test Mode became the first test technology that I worked on at Intel.

The technology started with an idea that Eitan Rosen, a design engineer at Intel’s Haifa campus, had for data retention failures. As explained in an introductory post, SRAM bit-cells can have defects that impact the cell stability which can manifest as a retention failure. The standard test procedure took a very functional approach: write a state, wait a long time, check if the state has changed. As a circuit designer, Eitan recognized that it takes a lot of circuit energy to write an opposite state. What if you yanked on the bit lines just a little to change the state to find defective cells?

Changing the state of an SRAM cell with the DFT circuit designed by E. Rosen
Changing the state of an SRAM cell with the DFT circuit designed by E. Rosen

The idea had been passed to the P54CS microprocessor team. I joined the Cache design team with the goal to implement Eitan’s design for test (DFT) circuit. As the idea was presented to the whole design team, Jash Banik thought about it and came up with an improved design. Let’s not just yank, let’s weakly write the opposite state. Like all innovation it built upon the previous design. I performed circuit simulations on both designs; Jash’s design had some advantages. We reviewed the results with Eitan and he concurred the new DFT circuitry had significant advantages. He would follow our design on his next project.

As a circuit designer who heard about the test challenges for data retention, Eitan had the knowledge to think about it differently. He came up with an alternative–let’s stress the SRAM cell so that only bad cells fail. It worked out really well and gave me an opportunity to work on a sexy hard problem. I have more stories to share regarding the Weak Write Mode Test Saga, here’s the introduction to this saga.

Have a productive day,

Anne Meixner

Dear Reader, What memory or question does this piece spark in you? Have you taken a different approach– wacky idea to solve a problem? Please share your comments or stories below. You too can write for the Engineers’ Daughter- See Contribute for more Information.

Additional Reading

Eitan Rosens’ Patent describes the circuitry.  Here’s a diagram illustrating the DFT circuitry.

Eitan Rosen’s DFT Circuit at bottom of the column of Memory cells.

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