Apprenticed to Study Manufacturing Defects–A Graduate School Story


In the Fall of 1988 I started my PhD studies in Electrical and Computer Engineering at Carnegie Mellon University. Soon, I began to have an inkling of why Professor Wojciech Maly had invited me to be his student.

Attending the weekly research group meeting exposed me to the thesis topics of the other students. Phil Nigh worked on an alternative means of testing for shorts in CMOS logic circuits. He measured power-supply current instead of checking the 1’s and 0’s produced from the applied test vectors. Derek Feltham explored the fault tolerance that VLSI implementation of neural networks exhibited. Samir Naik investigated extracting defect characteristics from SRAM testing, while Jitu Khare investigated test structures to characterize defects. PK Nag looked at the behavior of CMOS devices with opens. Defects touched everyone’s work.

A new language became ensconced in my mind as I began my apprenticeship. Much about a PhD program can be likened to the apprentice system used in the trades. You become attached to a master craftsman. At first all you do is sweep the shop and listen. Just hanging out you pick up on the language and the basic tools of the trade. Wojciech Maly had a very specific way of viewing faults. I still hear the following terms for “spot” defects in his brisk Polish accent:

  • Deformation – a containment falls on the VLSI design at a particular layer during manufacturing
  • Defect – a deformation changes the physical structure of the VLSI design
  • Fault – a defect results in a misbehavior of the circuit

In an apprenticeship you soon add other tasks to your shop sweeping duties. You may be helping another apprentice with her project. We regularly helped each other edit papers and prepare for oral presentations at conferences. During my first summer Wojciech asked me to look at process variation impact on operational amplifiers (op amps.) The resulting data could support a paper he was writing.

This small task introduced me to the fact that other manufacturing anomalies existed. Temperature distributions changed throughout a boat of wafers impacting oxide thickness. Uneven layer of photo resist had a radial pattern due to the spinning of a wafer. CMOS device voltage thresholds varied due to differences in implant energy of the doping devices. Basically, one could have two identical devices only microns apart on the wafer and they may not have identical manufacturing experiences–resulting in differences in electrical behavior of the “identical” devices. These revelations increased my entrancement with semiconductor manufacturing complexities.

So I now understood precisely the line in my graduate application that caught Wojciech’s attention:

“I’m fascinated by defects in the semiconductor process and the engineering aspects of design tolerance, and the preventing and detecting of them via test and diagnosis.”

I also understood what a good match I had found in being apprenticed to Professor Wojciech Maly. Stay tuned to learn about my PhD thesis topic.

Have a Productive Day,

Anne Meixner

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