Doug, the P54CS memory design manager, stated numerous times to not fail a good cell. My mantra during the design of the very first weak write test mode circuit became “thou shalt not fail a good cell.” To address this requirement, the boundaries between a good and bad cell needed to be determined. Given the methodology of weakly overwriting a cell I had to determine “weak” and “good” cell boundaries.

One can look at an SRAM cell as a latch and all latches can be put into meta-stability state. To comprehend the theory of Weak Write Test Mode (WWTM) operation I studied the SRAM cell’s meta-stability. Using a resistor, R, to model a defect I explored the changes in meta-stability behavior of the SRAM cell. Simulation results showed a difference in meta-stability characteristics. For a perfectly balanced cell it’s straight line. With a pure open, R equals infinity, the simulations showed a drastic difference. As the R decreased in value the meta-stability line approaches the straight line. From this study I could justify the boundary between a good and bad cell to be approximately 250 Kilo-ohms.

The following criteria guided the WWTM circuit design:

• Not overwriting a good cell
• Detecting open or weak connections in the p-devices
• Detecting weak p-devices

Simulating good cells during a weak write became my first task. I varied the WWTM circuit’s Mb and Ma device sizes until good cells failed. These simulations established a key design choice: Mb had the greatest impact in overwriting a good cell. The graph X illustrates the impact on WWTM operation. Detecting a symmetric defect, one that impacted both PMOS devices connections to Vcc- guided selecting Ma device size. Next, I looked at refining the circuit design with respect to finding asymmetric defects (varying the resistance from 0 to 500 Kilo-ohms).

Summarizing the design exploration, I used five lines to delineate the boundaries for each criterion:

1 – Does not overwrite a good cell at worse case corner;

2 – Does not overwrite a good cell at typical process corner;

3 – Flip a symmetric defect within 50 ns;

4 – In flipping symmetric defects, recover a stable ‘1’ state at the end of the 50 ns weak write signal;

5 – Detect 250 kilo-ohm minimum resistance for asymmetric.

The shaded regions in the plot indicate unacceptable designs. The white space represents acceptable designs. The two dashed lines cross at the sizes chosen for the final design and indicate the geometric distance from the boundaries. Yea! Design goal for WWTM circuit met!

In responding to the “Don’t Fail Good Cells” mantra, I explored the difference between good and bad SRAM cell behaviors to set reasonable boundaries. I had to assure that the faulty cells would be detected. However, if the WWTM circuit had failed good cells I would not have an effective solution.

Have a Productive Day,

Anne Meixner

Dear Reader, What memory or question does this piece spark in you? How have you balanced multiple design criteria for your solution? What kind of trade-offs between efficiency and effectiveness of a solution have you made? Please share your comments or stories below. You, too, can write for the Engineers’ Daughter–See Contribute for more Information.

Additional Reading

For more information on metastability read this page.

To learn some basis on semiconductor manufacturing you can read this overview on wikipedia.