Pathfinding Work on No-Touch Leakage Testing, Part 3: Tales from the Intel I/O Test Road Map

On Willamette we proved that AC I/O loopback testing worked. The AC I/O loopback provided the designers margin. I had completed the groundwork for testing I/O leakage on the structural tester using the RC decay leakage method (link to previous post.) Alas, we didn’t get a chance to try it out on the structural tester. The product engineering team had a full pin count tester to check I/O leakage; no need to risk a new method.

The vision to do all I/O testing on the structural tester continued on Prescott (Pentium 4 on 90 nm.) I worked with the I/O design team by coaching on defect-based methods. They improved upon the AC I/O Loopback implementation by developing methods to measure voltage levels. They even looked at how to test impedance compensation. For leakage, I recommended to the engineers that they consider a DC bias method as well as RC decay method to detect excessive I/O leakage. This idea had been invented by Tim Frodsham and David O’Brien, as they worked on Willamette I/O test strategy. No engineering team, though, had designed an implementation yet.

This DC bias method used elementary electrical circuit theory to measure leakage in terms of volts. Consider testing for Leakage to Vss; the tests are as follows:

  • Disconnect the drive source
  • Connect a leaker device to Vcc
  • Measure the voltage at the pin

By adding a set of leakage devices to create a voltage divider, leakage has been transformed to a voltage measurement. This makes it easy to measure on the die by using the I/O’s own comparator. The result can easily be transmitted to JTAG accessible register. Every electrical engineer learns Ohm’s law in their first class on circuits. I think it’s slick that this simple equation formed the basis of a new test method for I/O leakage.

As documented in their 2004 conference paper, the designers found via simulation that the driver leakage varied twice as much as the leaker devices. This impacts test accuracy, and hence setting the test limits for pass/fail. Like all test methods, the limits are guard-banded to account for measurement accuracy. The engineers performed a preliminary silicon validation on selected pins for several units. They mimicked different leakage values by forcing a current in or out of the unit pins. Their data showed that it could be an effective method. However, the final test program relied upon the full-pin count tester for leakage testing. The familiar won out over the new and different.

This three-part series on No-Touch Leakage pathfinding described how two different approaches had been developed. Simulation work showed them as capable. Limited empirical work had been done to verify that they worked, as no-touch leakage had lower priority. The introduction of High Speed Serial I/Os on Intel products forced the pursuit of a no-touch leakage solution. We had much to learn in implementing no-touch leakage. In the years 2003-2005 we were about to see how these worked in the factory. It would be a long road.

Have a Productive Day,

Anne Meixner

Dear Reader, What comments or question does this piece spark in you? Have you had to simulate to verify your solution?  Has the actual product matched your simulations? Please share your comments or stories below. You, too, can write for the Engineers’ Daughter- See Contribute for more information.

Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.