Three Patents for PLD–That was Good

Let me share my experiences with Programmable Logic Devices (PLDs). Intel had a small group down in Folsom working on this technology. Because of re-orgs, my wife and I moved to Folsom and we lived down for eight years (1988-1994). As part of that team I came up with  three patents.  And it was just fun work, we were a great team that I had helped build. On this one patent it was me and another guy Jay, he was the hardware side and I was the software side we were figuring things out, but I also have some hardware background.

Designers would really like to use more XOR logic and we were trying to make an XOR gate as fast as an AND gate.  That was the problem we wanted to solve, and we came really damn close.  We were shooting for 7.5 ns Tpd, from input to device output.  The 1991-1992 time frame we were on CMOS, and trying to cross over from an EPROM to a Logic process, but reprogrammable?  How do to this? It was another part of my group that basically helped Intel put FLASH on logic processes.

Back to the PLD side, customers wanted the XOR. We had identified several key applications that needed this kind of functionality– but how could we do with it what we had available in the technology? We worked together for three to four months, may have been longer. We finally came up with a design, actually built a chip, and we sold it. It was actually a product, and I still have one somewhere in my boxes.

People working together doing stuff.  It was a small team,  three of us on design, and another five to six as part of the whole product development team, acting as interfaces to other larger groups. That’s the satisfaction. That we came up with stuff; it worked; we made a product. While the first product wasn’t a good seller, it had value as a spear-head for a lot of the problems we had, and created a market presence for the group.

I can discuss the software to support the PLD configuration. The user interface that described how to configure there’s all the switches to configure. In some ways, the software components weren’t too complicated. Still you had to configure two switches per transistor and these switches were in the speed path. Recall, we had a goal to have the XOR be as fast as the AND. This story actually leads back to ease of use which is always important to me.  Because if it ain’t easy to use than nobody is going to use it. Or they will use it and but they’ll gripe about it and complain about it till something better comes along.

Was just one of those moments when you look back on a project and say “That was Good.” A couple of my patents were that way.

Have a Productive Day,

Richard Vireday

Dear Reader, please share your comments and stories that are sparked by this piece. So you have a collaboration with an another engineer that went so smooth that you can look back at and say “That was Good?” What have your innovation experiences been like? See Contribute for how you can share a story at The Engineers’ Daughter.

Additional Reading

PLA: Programmable Logic Array or Device (D), for an introduction read here and here.

The 3 patents discussed:

PAT. NO. Title
1 5,530,439 Deterministic method and an apparatus for minimal switch circuits
2 5,371,495 Deterministic routing method for minimal switch circuits
3 5,302,865 High-speed comparator logic for wide compares in programmable logic devices

FPGA: Field Programmable Gate Arrays evolved from the PLDs discussed in this post.

On the software side of things Richard used JTAG (1149.1) to do the programming, traditionally they had used a parallel interface.  This saved pins.

 

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