Predicting Fails for I/O Timings: Tales from the Intel I/O Test Road Map

While Spass and Mike measured actual I/O timing failures, I simulated possible defect causes and their impact on timing performance. I used techniques I honed in graduate school on deformations to circuit misbehavior. Process variation could hypothetically contribute to circuit timing fails, though analog circuit designers mitigated the impact of such variation to circuit performance….

Attributions in the Engineering Community—From the Weak Write Test Mode Saga

I had approximately 500 Pentium (P54CS) parts that uniquely failed the Weak Write Test Mode (WWTM.)  In the lab I ran the test on an IMS debug tester to diagnose the failing cell location–engineers always want more data. I talked to engineering managers regarding additional tests. The resulting list would require help from other engineering…

Diagnosis–Exactly Where and What is that Needle?

At IBM, I became fascinated with finding defects in semiconductor devices. For most of my professional life I have focused on testing for defects in a manufacturing setting. When in this setting, you want to determine yes or no; often referred to as “no/go” testing. The test is run–and if “no,” you stop, if “yes,”…

LOMAC Tester—Knowing Your Measurement Capabilities

Neither Chris nor I knew much about the LOMAC tester; Fred as the equipment owner did. It sure would have saved some work if we had talked with Fred. This is a story of how doing things in an incremental fashion creates more work. Efficiency is one of the E’s of engineering; it often requires…